The invention relates to programmable integrated circuit devices, more particularly to wide logic gates implemented in a single configurable logic element in a field programmable logic device.
Field Programmable Gate Arrays (FPGAS) typically include an array of tiles. Each tile includes a Configurable Logic Element (CLE) connectable to CLEs in other tiles through programmable interconnect lines. The interconnect lines typically provide for connecting each CLE to each other CLE. Interconnect delays on signals using these interconnect lines, even between adjacent CLEs, are typically much larger than delays on signals that remain within a single CLE. Therefore, it is desirable to implement a logic function in a single CLE whenever possible, rather than spreading out the logic into two or more CLEs.
CLEs typically include combinatorial function generators, which are often implemented as 4-input lookup tables. Some CLEs can also implement any 5-input function, and some wider functions, by selecting between the output signals of two 4-input function generators with another CLE input signal. One such CLE, implemented in the Xilinx XC4000(trademark)-Series FPGAs, is described in pages 4-11 through 4-23 of the Xilinx Sep. 1996 Data Book entitled xe2x80x9cThe Programmable Logic Data Bookxe2x80x9d, available from Xilinx, Inc., 2100 Logic Drive, San Jose, Calif. 95124, which pages are incorporated herein by reference. (Xilinx, Inc., owner of the copyright, has no objection to copying these and other pages referenced herein but otherwise reserves all copyright rights whatsoever.) A portion of an XC4000-Series CLE that can implement any 5-input function is shown in FIG. 1. The output signals Fxe2x80x2 and Gxe2x80x2 of the two function generators F and G can be optionally combined with a third input signal H1 in a third function generator 3H to form output signal 3Hxe2x80x2. (In the present specification, the same reference characters are used to refer to terminals, signal lines, and their corresponding signals.) The 3H function generator can implement any function of the three input signals (256 functions), including a 2-to-1 multiplexer that can be used when a 5-input function is desired. When function generators F and G share the same four input signals (F1/G1, F2/G2, F3/G3, F4/G4) and function generator 3H is programmed to function as a 2-to-1 multiplexer, output signal 3Hxe2x80x2 can represent any function of up to five input signals (F1/G1, F2/G2, F3/G3, F4/G4, H1). When the input signals driving function generators F and G are independent, output signal 3Hxe2x80x2 can represent some functions of up to nine input signals (F1, F2, F3, F4, G1, G2, G3, G4, H1).
For example, to implement a wide AND-gate in an XC4000-Series FPGA, all the function generators F, G, 3H can be configured as AND-gates, as shown in FIG. 2A. Function generators F, G are configured as two 4-input AND-gates, while function generator 3H is configured as a 3-input AND-gate. The resulting output signal 3Hxe2x80x2 is the 9-input AND-function of input signals F1-G4, H1, and F1-F4.
Similarly, as shown in FIG. 2B, a 9-input OR-gate can be implemented by configuring all the function generators F, G, 3H as OR-gates. The resulting output signal 3Hxe2x80x2 is the 9-input OR-function of input signals G1-G4, H1, and F1-F4.
Many other 9-input functions can be implemented in an XC4000-Series CLE. These wide logic functions are made possible only by the 3-input function generator 3H. Without the third function generator, the logic functions that can be implemented in a single CLE are much more limited. However, a 3-input function generator requires a great deal more silicon to implement than a more limited function such as, for example, a 2-to-1 multiplexer. Therefore, many CLEs do not include a third function generator as a supplement to a pair of 4-input function generators.
Function generator 3H can be replaced by a 2-to-1 multiplexer, with signal H1 selecting between output signals Fxe2x80x2 and F1. Replacing function generator 3H of FIG. 1 with a 2-to-1 multiplexer reduces the number of supported functions with up to nine input signals, but still provides any function of up to five input signals and reduces the silicon area required to implement a 5-input function generator. An FPGA using two 4-input function generators and a 2-to-1 multiplexer to implement a 5-input function generator is the XC3000(trademark) family of products from Xilinx, Inc. The XC3000 CLE is described in pages 4-294 through 4-295 of the Xilinx September 1996 Data Book entitled xe2x80x9cThe Programmable Logic Data Bookxe2x80x9d, available from Xilinx, Inc., which pages are incorporated herein by reference.
It would be advantageous to be able to implement certain wide logic gates using only two function generators. It is therefore desirable to provide structures and methods for implementing wide logic functions such as wide AND and OR-gates in a CLE while using only two function generators.
A first aspect of the invention provides a structure and method for implementing a wide AND-gate in an FPGA configurable logic element (CLE) or portion thereof that includes no more than two function generators. First and second function generators are configured as AND-gates. The output signals from the function generators (first and second AND signals) are combined in a 2-to-1 multiplexer controlled by the first AND signal. If all input signals to the first function generator are high, then the first AND signal is high, and the multiplexer passes the second AND signal. If at least one of the input signals to the first function generator is low, then the first AND signal is low, and the multiplexer passes the first AND signal, thereby providing a low multiplexer output signal. Therefore, a wide AND-gate is provided having a number of input signals equal to the total number of input signals for the two function generators.
Another embodiment of the invention provides a structure for generating other wide logic functions incorporating an AND function. For example, an OR-AND structure can be provided by configuring the first and second function generators as OR-gates, then using the 2-to-1 multiplexer (coupled as described above for the wide AND-gate) to AND together the output signals from the function generators.
A second aspect of the invention provides a structure and method for implementing a wide OR-gate in an FPGA CLE or portion thereof that includes no more than two function generators. First and second function generators are configured as OR-gates. The output signals from the function generators (first and second OR signals) are combined in a 2-to-1 multiplexer controlled by the second OR signal. If all input signals to the second function generator are low, then the second OR signal is low, and the multiplexer passes the first OR signal. If at least one of the input signals to the second function generator is high, then the second OR signal is high, and the multiplexer passes the second OR signal, thereby providing a high multiplexer output signal. Therefore, a wide OR-gate is provided having a number of input signals equal to the total number of input signals for the two function generators.
Another embodiment of the invention provides a structure for generating other wide logic functions incorporating an OR function. For example, an AND-OR structure can be provided by configuring the first and second function generators as AND-gates, then using the 2-to-1 multiplexer (coupled as described above for the wide OR-gate) to OR together the output signals from the function generators.
The invention allows the implementation of common wide logic functions in a single CLE. This efficient use of resources is advantageous. For example, two independent 8-input AND-gates can be implemented in a single CLE of a Virtex(trademark) FPGA from Xilinx, Inc.